A channel emulator is a specialized piece of electronic test equipment that emulates propagation of radio-waves based on well-defined environmental conditions. Channel emulators have been available for many years. Examples include the Spirent VR5 and the Anite Propsim. A channel emulator can emulate a reproducible set of environmental conditions that allows the verification of radio performance, as well as comparative evaluation of different radios under identical (emulated) propagation conditions. Traditional channel emulators were designed for conventional radios, now referred to as single input single output (SISO) radios. A SISO channel emulator models a single fading channel between a transmitter and a receiver by emulating multipath and Doppler fading in a multitude of predefined environmental conditions described by channel models. Multipath is a phenomenon whereby a transmit signal reflects from multiple surfaces and arrives at the receiver in the form of a sum of multiple delayed versions of itself. Multiple versions of the same transmit signal add together either constructively or destructively, resulting in time-variable signal attenuation known as multipath fading. Multipath fading creates signal fluctuation vs. time and this fluctuation determines the channel's Power Delay Profile (PDP). Models of representative PDPs of fading channels (e.g. inside of a house or urban environment) are defined by industry standards, such as, for example, 3rd Generation Partnership Project (3GPP) TR 25.996, “3rd Generation Partnership Project; technical specification group radio access networks; Spatial channel model for MIMO simulations”, which is hereby incorporated by reference.
An example of a PDP plot (signal power vs. time) is shown in FIG. 6. Standards based channel models typically define PDPs as being composed of one or more reflection ‘clusters’. A cluster can be a group of electromagnetic ‘rays’ reflected together from a surface such as, for example, a wall or a corner of a room. In a typical wireless channel, multiple such clusters separated in time combine to create a PDP, such as the PDP shown in the plot of FIG. 6.
The delay spread of multipath reflections is a function of the size of the physical environment being modeled. Delay spread is shorter for small spaces (e.g. a small office) and longer for large spaces (e.g. outdoor environments).
A typical channel emulator downconverts the RF signal transmitted by a device under test (DUT), digitizes this signal into a stream of in-phase and quadrature (IQ) samples and mathematically processes the digitized IQ streams according to a selected multipath and Doppler fading model. The resulting signal is then upconverted and coupled into the receiving device under test (DUT).
Modern 2-way data communications radios, such as IEEE 802.11n and 3GPP Long Term Evolution (LTE) radios, use Multiple Input Multiple Output (MIMO) technology. A MIMO radio is composed of multiple receive and transmit subsystems (chains) operating in phase lock and employing sophisticated radio transmission techniques to increase data throughput and operating range of wireless links. A MIMO link is typically described as an N×M link, where N is the number of transmit chains in a transmitting radio and M is the number of receive chains in the receiving radio. In a MIMO link signals from all N transmit chains couple into each of the M receive chains via correlated MIMO paths in an airlink (e.g. in a room). Therefore, a MIMO channel emulator must model N times M fading channels (as compared to a SISO emulator that models only one fading channel). In prior art channel emulators each fading channel is typically implemented as a tapped delay line (TDL) structure, as shown in FIG. 2. Channel models specifying the time-variable tap coefficients for the TDL multipliers and correlation of these coefficients are defined by industry standards being developed by organizations, including IEEE and 3GPP. Channel models can also be defined by end users or recorded for real environments using channel sounding techniques.
In prior art channel emulator implementations the number of fading channels grows exponentially with the number of ports. For example a 2×2 MIMO channel emulator has 4 fading channels, Hij, as shown in FIG. 3. A 4×4 MIMO channel emulator has 16 fading channels, Hij, as shown in FIG. 4.
A unidirectional MIMO channel emulator for an N×M MIMO system has N receive and M transmit ports. The transmitting DUT connects to the N receive (input) ports of the channel emulator and a receiving DUT connects to the M transmit (output) ports of the channel emulator. If the channel being modeled is bidirectional, a channel emulator typically duplicates the circuitry in the forward and reverse directions to accommodate 2-way transmission between the DUTs, as shown in FIG. 5. The DUT RF ports, which for normal operation connect to antennas, are typically bidirectional. Thus, RF circulators or diplex filters must be used to separate transmit from receive signals for coupling to the channel emulator input and output ports, as shown in FIG. 5. Circulators are used when DUTs use the same frequency for transmitting and receiving, as do, for example, Wi-Fi or TDD (time division duplex) DUTs. Diplex filters can be used to separate RX from TX signals when DUTs use different transmit and receive frequencies, as do, for example, FDD (frequency division duplex) DUTs.
Prior art channel emulators incorporate RF front end and a Digital Signal Processing Subsystem (DSPS), as shown in FIG. 1. Prior art implementations cost hundreds of thousands of dollars because they implement a full mesh of fading channels: from each input port of a channel emulator to each output port. Thus, the complexity and cost of the DSPS computational hardware increases exponentially with the number of ports.
In prior art implementations, for each MIMO input the RF signal is downconverted to baseband and then digitized to produce IQ sample streams. Then channel models are applied computationally to the IQ streams in real-time by the DSPS.
In modern MIMO channel emulator implementations, DSPS computing logic incorporates thousands of complex 16-bit multipliers operating at clock speeds of up to 400 MHz and typically implemented in FPGAs (field programmable gate arrays).
Each TDL that implements a fading channel is comprised of complex multipliers, as shown in FIG. 2. A 4×4 MIMO channel emulator has 16 fading channels and each fading channel is implemented by a TDL. Each tap in a TDL is a complex multiplier requiring 4 hardware multipliers.
To model a 40 MHz wireless channel, as for example is required for 802.11n systems, the IEEE 802.11 specification for channel modeling, “IEEE 802.11-03/940r4, TGn Channel Models” document, which is hereby incorporated by reference, requires up to 18 taps per TDL. To model an 80 MHz channel, as for example is required for 802.11ac channel emulation per “IEEE 802.11-09/030r10, TGac Channel Model Addendum” document, which is hereby incorporated by reference, the number of taps per TDL and hence the number of complex multipliers is up to 35 per TDL. For 802.11ac systems using 160 MHz RF channel, the number of taps up to 69. To implement an 802.11ac 8×8 channel emulator, the number of fading channels, H, is 8*8=64. The number of taps per fading channel (per TDL) for 160 MHz wide channel is 69. Thus, the number of complex multipliers required to implement a DSPS of an 8×8 MIMO 802.11ac channel emulator supporting 160 MHz wide channel is 64 paths*69 taps per path=4416. And each complex multiplier is comprised of 4 hardware multipliers. Thus the total number of multipliers operating simultaneously and clocked by a 400 MHz clock is 4416*4=17,664. For a bi-directional implementations the number of multipliers is doubled for implementing each direction of the signal flow, requiring 17,664*2=35,328 multipliers. Implementing such a DSPS would require multiple state-of-the art power-hungry FPGAs performing 35,328 simultaneous multiplications at the rate of 400 MHz. With today's FPGA technology, this computational requirement borders on infeasible. And, as indicated above, the number of such computationally intensive fading channels implemented in a DSPS increases exponentially with the number of channel emulator ports. Channel emulators for future MIMO systems of higher order than 8×8 will be extremely challenging to implement using prior art computational techniques since the required number of multipliers grows exponentially with the number of channel emulator ports.
Analog or RF based channel emulation implementations, such as the invention described in this disclosure, are considerably more practical and economical.
At the output of a prior art DSPS, digital IQ streams, which have multipath computationally applied to them by the DSPS, are converted to analog using D/A converters and then the analog IQ signals are upconverted to RF carrier frequency, creating the RF output from the channel emulator to the receiving DUT, as shown in FIG. 1 and in FIG. 5.
The reference to prior art, documents and other things known to those skilled in the art is not intended by way of likeness or differentiation from the present inventions, but is rather mentioned as an aid to those of interest and skill in the art to set a context for the inventions. Any such documents and things are hereby incorporated by reference.